DFT Engineer

About Unconventional 

Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented demand for computation—a demand that is now fundamentally limited by energy, not just in the datacenter, but at a global scale.

At Unconventional, our mission is to solve this. We are rethinking computing from the ground up to build a new foundation for AI that is 1000x more efficient. We're doing this by exploiting the rich physics of semiconductors, mapping neural networks directly to the device physics rather than relying on layers of inefficient abstraction.

The Role

As a Member of Technical Staff, DFT Engineer, you will be a foundational member of our multi-disciplinary R&D team. We are looking for individuals who thrive at the intersection of architecture and silicon, turning novel AI concepts into high-performance, energy-efficient hardware. You will be responsible for the testability realization of our novel computing platform, ensuring that our complex digital logic and custom mixed-signal blocks can be reliably tested.

Responsibilities

• DFT Architecture & Implementation: Lead the implementation of comprehensive test architectures using industry-standard CAD tools. This includes the insertion, configuration, and verification of scan compression, Memory Built-In Self-Test (MBIST), and JTAG/boundary scan logic.
• Hierarchical DFT Implementation: Drive bottom-up hierarchical DFT methodologies for large-scale SoC designs, managing core-level test wrapping, pattern retargeting, and top-level test integration to optimize runtime and capacity limits.
• Foundry Interface & Defect Analysis: Own the overarching DFT strategy, working closely with foundry interfaces to analyze defect densities and drive yield improvements for test chips.
• Multi-Stacked Die DFT: Drive cutting-edge DFT methodologies for 2.5D/3D multi-stacked die packaging. You will ensure comprehensive test coverage across die-to-die interfaces utilizing emerging standards like IEEE 1838.
• Analog Macro DFT: Work at the interface of digital and analog design to facilitate the integration and testability of custom analog mixed-signal blocks. You will develop novel test strategies for non-standard analog macros operating within the digital fabric.
• Test & PPA Optimization: Drive aggressive test coverage, test time, and yield targets while working closely with architects to influence the micro-architecture for better Power, Performance, and Area (PPA).