Photonics Integrated Circuit Engineer

Job Description

The Lead Photonics & Quantum Integration will own the technical strategy, execution, and roadmap appendices covering photonic interconnect, integrated silicon photonics, single-photon source integration, and longer-horizon quantum–classical hybrid compute elements within the programme’s technology roadmap. The successful candidate will bridge deep expertise in quantum photonics device physics with the practical demands of semiconductor process integration, working closely with the device teams to identify co-integration opportunities on the shared hardware platform. As a senior photonics engineer you will take ownership of the physical design and verification of cutting-edge photonic integrated circuits (PICs), guiding designs from initial proof-of-concept phases to high-volume manufacturing readiness.

Key Responsibilities

Roadmap & Strategy

• Lead the Photonics technology roadmap aligned with the programme’s overall progression.
• Define go/no-go decision criteria, risk registers, and cost models for photonic integration at each process node, consistent with the programme’s existing MPW and pilot-line budgeting methodology.
• Conduct technology horizon scanning and competitive landscape analysis across silicon photonics, photonic quantum computing, and optical interconnect for AI accelerators.

Device & Process Integration

• Lead the design, simulation, and characterisation of photonic components (waveguides, modulators, photodetectors, single-photon sources) compatible with the programme’s FEOL + X + BEOL process flow. Layout Execution & Tape-out Ownership: Lead complex, full-loop manual and automated layout designs and mixed-signal functions (high-speed/general I/Os, ESD structures). Drive the full tape-out process, including floor planning, waveguide routing, and mask data preparation.
• Design and simulate photonic integrated circuits for communication, sensing, or compute-related applications. Work with fabrication partners to develop layouts and ensure manufacturable designs. Collaborate with electronics, packaging, and test teams to integrate PICs into larger hardware systems.
• Verification & Mitigation: Execute rigorous post-layout verification (DRC, LVS, fill, density) across multiple stepping versions. Trace defect sources, mitigate layout-dependent issues, and ensure DRC/LVS cleanliness prior to tape-out.
• Evaluate and specify co-integration pathways for photonic elements with the existing HZO ferroelectric and metal-oxide layers, identifying shared ALD and BEOL metal-stack process steps.
• Develop optical test and characterisation methodologies from wafer-level through to packaged sub-assembly, defining pass/fail metrics for manufacturing readiness.