FPGA Developer
Posted 29 Jan 2026
Advertised as “Senior FPGA Developer (SystemVerilog)”
BranchFactor Summary
The original posting with the fluff stripped out
- Expected experience
- 5+ yrs
- Management level
- People management
- Employment
- Hybrid
- Visa sponsorship
- Not offered
No salary listed for this role.
The Role
The Senior FPGA Developer will be a member of the core team building the Quantum Key Distribution system. The focus is end‑to‑end RTL ownership on AMD/Xilinx (Artix‑7, Kintex UltraScale): architect, implement, verify, and close timing on high‑rate interfaces and deterministic pipelines. The role also sets engineering discipline for FPGA development and mentors a junior engineer.
The Senior FPGA Developer owns the FPGA architecture/codebase and collaborates closely with embedded/software to define clean contracts, ensure reliable bring‑up, and deliver reproducible, versioned bitstreams.
The Responsibilities
The Senior FPGA Developer should expect to work in the following activities.
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RTL architecture, interfaces, and rather high-speed datapaths
- Owning SystemVerilog RTL architecture/implementation for Artix‑7 and Kintex UltraScale (SystemVerilog, Vivado)
- Implementing DDR3/DDR4 controllers integration, PCIe endpoint/DMA, and Ethernet/SFP paths; evaluating/integrating third‑party MAC/PCS IP
- Building deterministic acquisition/timing/sifting layers — packetization, buffering, alignment; robust clocking/CDC/reset; custom low‑level protocols — and bridging them to high‑throughput interfaces (DDR/PCIe)
- Defining clear AXI/AXI‑Stream boundaries and register maps for SW/FW integration
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Constraints, timing closure, and floorplanning
- Authoring and maintaining XDC constraints (clocks, I/O, exceptions); achieving consistent timing closure across corners
- Applying practical floorplanning (pblocks, placement guidance) and CDC methodology; analyzing reports and iterating for margin
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Verification and CI
- Establishing a professional verification environment with ModelSim/Questa; developing self‑checking testbenches and regression suites; integrating Python/cocotb co‑simulation with software harnesses/mocks; defining coverage goals (OSVVM/UVM as appropriate)
- Building CI for lint/sim/synth/impl; archiving reports/bitstreams; automating regressions (including cocotb) and basic HW‑in‑the‑loop smoke tests
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Bring-up, debug, and releases
- Board bring-up and debug using ILA/logic analyzers; link training, memory calib, and protocol bring-up
- Owning bitstream packaging, versioning, and release notes; ensuring reproducible builds and traceable artifacts
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Cross-team collaboration and mentoring