Micro-Optics Engineer
Posted 23 Jul 2026
BranchFactor Summary
The original posting with the fluff stripped out
- Management level
- Individual contributor
- Employment
- Remote
No salary listed for this role.
Field of studyApplied Physics, Electrical Engineering, Materials Science, Mechanical Engineering, Optical Engineering, Photonics, Physics (or related)
Study levelBachelor's or higher
Role Overview
We are seeking a Senior Micro-Optics/Microlens Array Engineer to design, model, and validate microlens-array and wafer-level micro-optical components for high-density photonic packages. You will translate system-level optical requirements into manufacturable designs, build tolerance budgets, work with fabrication and packaging partners, and close the loop with measured data.
Candidate note: We do not expect one person to match every item below. Strong candidates from micro-optics, optical packaging, semiconductor photonics, lithography/process integration, precision optics, or FDTD-Zemax co-design backgrounds are encouraged.
What You Will Do
- Own micro-optical design: design microlens arrays and compact micro-optical components, including lens pitch, aperture, focal length, numerical aperture, sag, surface form, fill factor, array uniformity, substrate, material, and coating choices.
- Build connected optical models: use tools such as Zemax OpticStudio, Code V, FRED, LightTools, VirtualLab, Ansys/Lumerical, COMSOL, or equivalent; combine ray, physical-optics, diffraction, and statistical methods where appropriate.
- Bridge EM-scale and package-scale design: where useful, connect FDTD, FEM, EME, RCWA, or similar electromagnetic simulations to Zemax/Code V/physical-optics models so local optical-interface behavior is represented in system-level trade studies.
- Drive tolerancing and yield: develop sensitivity studies and tolerance budgets across fabrication, placement, package stack-up, adhesive, thermal, refractive-index, coating, and surface-form variation; use Monte Carlo and DOE methods to connect design choices to expected yield.
- Bring semiconductor process awareness: partner with process and supplier teams across lithography, grayscale/direct-write patterning, imprint, etch transfer, deposition, thin-film coatings, wafer-level metrology, design rules, and process-window trade-offs.
- Translate design intent: create vendor-ready specifications, optical prescriptions, mechanical drawings and guidance, material and coating requirements, metrology plans, incoming inspection criteria, and acceptance criteria.
- Partner with suppliers: evaluate fabrication routes such as photoresist reflow, grayscale lithography, etch transfer, molding, and replication.
- Validate hardware: plan and run prototype characterization, including surface profile, focal length, array uniformity, optical throughput, reflection behavior, polarization sensitivity, thermal drift, environmental stability, and alignment sensitivity.