CPU Core Design Verification Testbench

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

At Tenstorrent, we build open, state of the art compute for real workloads and real developers.

You will own CPU core-level testbench development and verification, shaping how our out-of-order RISC-V CPUs behave in silicon.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are 

• You bring 8+ years in CPU verification, CPU testbench development, or closely related digital design.
• You have deep hands-on experience building and owning CPU core-level testbenches, not just using existing environments.
• You know high-performance out-of-order CPU microarchitecture in depth.
• You are comfortable developing testbench infrastructure in CVM methodology, with UVM experience as a strong plus.
• You work comfortably across RTL, waveforms, logs, regressions, and cross-functional debug with design, DV, emulation, and post-silicon teams.
• You are comfortable using AI-assisted verification workflows to improve debug, stimulus creation, and coverage analysis, while applying strong engineering judgment to validate results.

What We Need 

• Lead hands-on CPU core-level testbench development for high-performance out-of-order RISC-V cores.
• Own and evolve CVM-based verification methodology, infrastructure, and reusable testbench components.
• Plan and drive functional verification for CPU core features, ISA behavior, and microarchitectural scenarios.
• Develop UVM, assembly, C/C++ stimulus, and C++ functional models for RISC-V extensions and un-core components such as APIC and IOMMU.
• Debug regressions, close coverage, and improve core, cluster, and chip-level testbenches across simulation, emulation, and post-silicon environments.
• Develop testbench and tooling infrastructure that combines Python orchestration with specialized AI agents to accelerate triage and root-cause analysis across logs, waveforms, and verification databases.