Interconnect and Compute Architect

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is seeking an Interconnect and Compute Architect  to help define and build next-generation CPU networking architecture for both datacenter and emerging robotics/automotive applications. You will contribute to our current datacenter networking efforts while also helping to seed and specify future medium- to low-power robotics/automotive devices for AI/ML compute and sensor ingest. The initial focus will be datacenter networking, with robotics as the first target within the automotive/robotics space.

This role is remote, based out of North America.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You thrive while navigating multiple priorities and ambiguous, evolving requirements.
• You have knowledge of Ethernet  network architecture and how performance is modeled.
• You have experience with die-to-die interfaces and understand associated protocols and design tradeoffs.
• You understand Ethernet networking concepts and how they map onto on-chip and off-chip fabrics
• You have experience with datacenter scale up architectures like UALink, NVLink, and Broadcom SUE.
• You have experience with scale out RDMA protocols like RoCE, Infiniband, and others.

What We Need

• A Interconnect and Compute designer who can contribute to both datacenter networking.
• Someone comfortable with the intersection of forwarding, buffering, modeling and RTL design to guide architectural decisions
• An engineer who can collaborate across hardware, software, and systems teams to define and refine networking requirements.
• A contributor who can help drive forward next-generation CPU networking architecture for AI/ML workloads.

What You Will Learn

• How to build next-generation CPU networking architectures for both high-performance datacenters. 
• AI/ML specific protocols and implementations. 
• Learn how to build extreme low latency networks across ethernet topologies and high performance computing (HPC) topologies.