ASIC Physical Design Director

We are seeking an experienced and visionary Director of ASIC Physical Design to strategically lead and direct our global physical design engineering teams. This pivotal role involves driving the physical implementation of complex ASICs from RTL to GDSII, with a strong emphasis on achieving optimal performance, ultra-low power, and area (PPA) targets on the latest technology nodes. The successful candidate will be responsible for defining advanced physical design methodologies, managing and developing teams across the USA, India, and Italy, fostering innovation, and collaborating closely with cross-functional engineering groups to deliver high-quality, manufacturable silicon, ensuring first-pass success under aggressive schedules.

Responsibilities

• Strategic Leadership & Global Team Management: Define and execute the physical design roadmap, strategy, and technical direction for multiple ASIC projects, aligning with overall product and technology goals. Lead, inspire, and strategically manage a distributed team of physical design engineers across the USA, India, and Italy.
• Team Development & Training: Mentor, grow, and build a high-performing global team, fostering a culture of technical excellence, collaboration, and continuous improvement. Specifically, drive the training and adoption of advanced methodologies, including the introduction and implementation of Customer Owned Tooling flow to ensure efficient and robust GDSII release.
• Advanced Methodology & Flow Development: Drive the development, adoption, and continuous improvement of cutting-edge physical design methodologies, flows, and best practices, particularly for advanced and latest technology nodes with a strong focus on low-power design techniques.
• Project Execution & PPA Optimization: Oversee the complete physical design cycle, including floor-plan, power grid design, placement, clock tree synthesis (CTS), routing, timing closure (STA), power integrity (IR/EM), physical verification (DRC/LVS), and DFM/DFY. Ensure all physical design activities are optimized to achieve aggressive PPA targets (performance, ultra-low power, area) for complex digital and mixed-signal ASICs on leading-edge process technologies.
• Cross-Functional Collaboration for First-Pass Silicon: Partner effectively and interact heavily with architecture, RTL design, DFT, CAD, package, and test teams to ensure seamless integration and successful first-pass silicon under tight development schedules. Proactively identify and resolve inter-team dependencies and technical challenges.