Member of Technical Staff - Microarchitect / RTL Design

About Architect Labs

Architect is a frontier AI lab for custom silicon. We partner with frontier labs, clouds / neoclouds, physical AI companies, and advanced fabs to tape-out custom chips co-designed for next-generation AI workloads. Our goal is to compress end-to-end software to silicon timelines, and maximize intelligence per watt and per dollar for the world. We are a small exceptional team across silicon, systems, software and frontier AI. Our team have led research teams at nearly every frontier AI lab, and at some of the most complex SoCs in the world.

What You'll Do

As a Member of the Technical Staff on the RTL Design team at Architect, you'll own the AI-driven microarchitecture and RTL design of mission-critical SoC blocks and sub-systems (SS) going into production silicon. You will be expected to define, drive, and revise the block-level micro-arch specification for one of the fundamental HW accelerator blocks.

As such, you fit our current opportunities if you have hands-on design and block-owner experience in any of the following ASIC components: on-chip memory SS, on-chip interconnect SS (NoCs, DMAs, etc.) with custom or standard protocols (AXI, etc.), IO and peripherals integration (PCIe, DDR, CXL, etc.), CPU/Host/controllers, Security, Compression, Debug/DFT (BIST, MBIST, etc.), and specialized accelerators such as ML/AI accelerators (NPUs, TPUs, etc.), SIMD vector engines, DSPs, GPUs, graphics/audio pipelines.

As a lab, we are investing in building a world-class HW design team, so if you think you have a particular experience/background that is not listed here, please still reach out to us!

• Own AI-driven RTL design flow end-to-end (at the frontend): through code generation to incorporating feedback from lint, CDC, synthesis, and timing closure stages for closing the design loop.

• Work directly with the principal architect to refine microarchitectural specs, resolve implementation trade-offs, and feed area/timing/power realities back into the architecture and internal AI systems.

• Define and maintain interface specifications (e.g. AXI, AXI-Stream, or custom-built) for block- and SS-level integration.

• Build and maintain RTL infrastructure for our in-house AI-driven flow: design automation scripts, regression flows, lint/CDC waivers, and integration collateral.

• Close collaboration with DV: Support DV bring-up with reference models, assertions, test-plans, and architectural documentation for verification closure.

• Close collaboration with SW and ML: Support and guide our SW and ML experts to revise and improve our in-house AI flow based on your own experience.