Design Verification Engineer
US$160,000 / yr base salary
Posted 23 Sep 2026
Advertised as “Senior or Staff Design Verification Engineer”
BranchFactor Summary
The original posting with the fluff stripped out
- Management level
- People management
- Employment
- Hybrid
- Contract
- Full-time
| Base salary | US$160,000 / yr |
|---|
Design Verification Lead
Reports To: Head of Engineering
About Us
Powerlattice is a well-funded semiconductor start-up company backed by leading Silicon Valley venture capital firms. We are developing groundbreaking chiplet power delivery technology that will transform how high-performance processors are powered, enabling the next generation of AI and advanced computing.
About the Role
We are seeking an experienced and hands-on Design Verification Lead to spearhead verification activities for complex SoC/IP designs, developing scalable SystemVerilog-based verification environments, verification strategies, reusable test infrastructure, and automated regression flows. This position drives functional verification from RTL through gate-level simulation, including coverage closure, assertions, timing verification, and debug. They will collaborate closely with RTL, analog, architecture, and silicon validation teams to identify and resolve design issues.
Key Responsibilities
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Lead verification planning and execution for complex digital and mixed-signal subsystems, including defining verification strategies, test scenarios, coverage goals, and signoff criteria.
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Architect, develop, and maintain SystemVerilog-based verification environments and reusable verification infrastructure.
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Develop directed, constrained-random, regression, and corner-case tests to verify functional requirements and design specifications.
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Develop reusable verification components and protocol-based test infrastructure for I2C/I3C, SPI, JTAG, AMBA, and OBI interfaces.
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Perform and support Clock Domain Crossing (CDC) verification for async and sync clock-domain interfaces.
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Develop and maintain UVM-based infrastructure and RAL models where applicable.
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Develop checkers, scoreboards, reference models, assertions, and functional coverage to provide comprehensive verification of design behavior.
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Perform RTL and gate-level simulation, including SDF-annotated GLS, to identify functional, timing, initialization, reset, and connectivity issues.
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Develop and optimize regression and GLS flows using Xcelium and VCS.
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Analyze functional and code coverage and drive coverage closure by identifying verification gaps and developing targeted tests.
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Debug complex RTL, testbench, simulation, and gate-level failures using waveform and log analysis.