3D Stacked Logic Design Engineer

About SK hynix America:

At SK hynix America, we are at the forefront of semiconductor innovation. As a global leader in HBM, DRAM, and NAND flash technologies, we develop the advanced memory solutions powering everything from advanced mobile technology to massive AI data centers. With major investments in the U.S. and a leading position in the global AI revolution, we build the critical infrastructure of the digital landscape and remain committed to sustainable operations. We invite innovative minds to be part of our journey. Here, you will be part of a collaborative team pioneering the next generation of memory technologies, expanding our market footprint, and defining the future of computing.

Work Model: Onsite

Job Title: 3D Stacked Logic Design Engineer
Office Location: San Jose, CA
Job Type: Full-Time
Work Model: Onsite 

Job Summary:

To strengthen leadership in the DRAM-on-Logic era through optimized DRAM die design, we are seeking talent capable of driving the co-design of 3D-stacked DRAM logic dies in close collaboration with U.S.-based customers. This strategic hiring initiative aims to enhance our global competitiveness by fostering deep engagement with key American clients, ensuring that our die design solutions are precisely aligned with their evolving technical requirements and market demands.

Responsibilities:

• Strengthen leadership in the DRAM-on-Logic era through advanced digital IP design for 3D-stacked DRAM.
• Provide digital IP services for 3D-stacked DRAM to enable DRAM-on-Logic system configurations for customers.
• Co-design 3D-stacked DRAM Logic Dies with U.S.-based customers.
• Improve competitiveness through close engagement with customers in the U.S.
• Design high-speed digital IP for 3D-stacked DRAM peripheral circuits and DRAM DFT with U.S.-based customers, covering RTL design to implementation.
• Conduct foundry verification of service-ready IPs and setting up infrastructure for the IP business.
• Deliver services to ensure seamless IP integration in customer design environments.
• Design digital logic blocks for 3D-stacked DRAM peripherals and Design-for-Test (DFT) features.
• Establish close technical engagement with key U.S.-based customers to address immediate 3D-stacked DRAM requirements.
• Establish close technical engagement with foundry partners (e.g., TSMC, Intel) to build digital IP for 3D-stacked DRAM.