AI Silicon, Design Verification
Posted 6 Apr 2026
BranchFactor Summary
The original posting with the fluff stripped out
- Expected experience
- 8+ yrs
- Management level
- Individual contributor
- Employment
- Remote
No salary listed for this role.
Field of studyComputer Engineering, Computer Science, Electrical Engineering (or related)
Study levelBachelor's
Field of studyComputer Science, Electrical Engineering
Study levelMaster's or higher
About Unconventional:
Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented demand for computation - a demand that is now fundamentally limited by energy, not just in the datacenter, but at a global scale.
At Unconventional, our mission is to solve this. We are rethinking computing from the ground up to build a new foundation for AI that is 1000x more efficient. We're doing this by exploiting the rich physics of semiconductors, mapping neural networks directly to the device physics rather than relying on layers of inefficient abstraction.
Responsibilities:
- Verification Strategy & Architecture: Define, architect, and implement comprehensive verification plans and environments for IP blocks and full chip from specification to tape-out.
- Methodology and Infrastructure: help build verification infrastructure from ground zero to flexible and nimble environments, able to move quickly and scale for growth.
- Testbench Ownership: Take full ownership of the verification lifecycle, including the development and maintenance of scalable testbenches, sophisticated test cases, and robust verification environments.
- Advanced Methodology Execution: Deploy industry-standard methodologies (UVM/SystemVerilog) to conduct constrained-random stimulus generation, coverage-driven verification, and assertions.
- Cross-Functional Integration: Collaborate closely with digital and analog design teams, as well as software and systems teams, to define verification requirements, debug complex hardware/software interactions, and ensure design integrity.
- Analysis & Closure: Perform exhaustive analysis of functional and code coverage. Debug failures at the RTL and gate level to ensure 100% verification closure and high-quality silicon.
Minimum Qualifications
- Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- Experience: Minimum of 8 years of hands-on experience with advanced verification methodologies and languages, specifically UVM and SystemVerilog.
- Technical Expertise: Proven track record of developing and maintaining complex verification testbenches and automated test environments.